Memory cells which have members that may be electrically charged are well-known in the prior art. Most often, these cells employ polysilicon floating gates which are completely surrounded by insulation (e.g., silicon dioxide). A charge is transferred to these floating gates through a variety of mechanisms such as avalanche injection, channel injection, tunnelling, etc. The charge on the floating gate affects the surface channel conductivity in the cell. If the conductivity is above a certain level, the cell is deemed to be programmed in one binary state, and if the conductivity is below another level, it is deemed to be programmed in the other binary state. These cells take a variety of forms in the prior art, some being both electrically erasable and electrically programmable, and others requiring, for example, ultraviolet light for erasing. The cells are incorporated into memories referred to in the prior art as EPROMs, EEPROMs, flash EPROMs and flash EEPROMs.
In general, an EPROM or an EEPROM is characterized by a substrate region including source and drain regions which define a channel therebetween. Disposed above this channel is a floating gate separated from the substrate region by a relatively thin gate insulative material. Typically, a layer of silicon dioxide is employed. A control gate is disposed above, and insulated from, the floating gate. The control gate is also commonly fabricated of polycrystalline silicon, i.e., polysilicon.
An example of a flash EEPROM cell is provided in FIG. 10 of U.S. patent application entitled "Low Voltage EEPROM Cell", Ser. No. 07/253,775, filed Oct. 5, 1988, still pending, which application is assigned to the assignee of the present invention. The principle upon which the EEPROM cell of FIG. 10 operates is that electrons (i.e., charge) are stored on the floating gate in a capacitive manner.
By way of example, during programming of the EEPROM device, the control gate is taken to a high positive potential ranging between 12 and 20 volts. The source is grounded and the drain is taken to an intermediate potential of approximately 7 volts. This creates a high lateral electric field in the channel region nearest to the drain. The high lateral electric field (i.e., "E-field") accelerates electrons along the channel region to the point were they become "hot". These hot electrons create additional electron-hole pairs by impact ionization. A large number of these electrons are attracted to the floating gate by the large positive potential on the control gate.
During erasing of the EEPROM device, the control gate is grounded and the drain is left unconnected (i.e., floating). The source is taken to a high positive potential around 12 Volts. This creates a high vertical E-field from the source to the control gate. Charge is erased from the floating gate by the mechanism of Fowler-Nordheim tunnelling of electrons through the gate oxide region between the source and the floating gate in the presence of such a field.
Note that in the memory cell of FIG. 10 of the above-referenced application, the source region is deeper and more graded when compared to the drain region. Observe also that the source region, because of its graded profile, extends further under the floating gate. The primary reason why the drain is fabricated to be shallower and more abrupt than when compared to the source is that hot electron generation is lateral channel E-field dependant. Thus, the drain region is intentionally given an abrupt junction to generate a high electric field in order to create a large supply of hot electrons.
On the other hand, the source region is graded to decrease the local electric field strength across the source/substrate junction during erase. This allows a 12 Volt or higher voltage to be applied to the source for erasure without breakdown. Note that while hot electron programming is entirely lateral channel E-field dependant, tunnelling from the source region is subject to vertical E-field control, which is tunnel oxide thickness dependant.
One problem that arises with electrically programmable memory cells of the variety described above is the unintentional disturbance to the drain region of an adjacent cell. This adjacent cell is usually located in the same column as is the cell which is being programmed. By way of example, when arranged in rows and columns, adjacent cells within a particular column will often have their drain terminals connected to a single column line.
To program an individual cell within a column, the common column line is raised to a high potential. The sources of the cells are grounded. The selected cell to be programmed has its control gate raised to a high positive potential while all other cells within that column have their control gates grounded. Drain disturbance refers to the phenomena by which adjacent cells within a column may become partially or totally erased as a result of the programming potential being applied to the drain regions along the common column line connected to those cells.
To penalize such "erase-like" behavior in these adjacent cells, the gate oxide separating the substrate from the floating gate can be thickened. While such thickening has no affect on hot electron programming characteristics, it does reduce erasing efficiency--which is strongly gate oxide thickness dependant. Thus, while it is desired to optimize erase capabilities from the source region by maintaining the gate oxide thickness as thin as possible, it is also desired to thicken the gate oxide nearest the drain region to prevent drain disturbance phenomena. Therefore, what is needed in the art is a process for reducing drain disturbance during programming without interfering with the erasing characteristics of the cell.
As will be seen, the present invention provides a method by which the gate oxide may be selectively thickened over the channel region nearest to the drain so as to penalize erase-type behavior leading to drain disturbance. At the same time, the gate oxide thickness nearest to and/or directly over the source region is maintained as thin as possible to maintain fast erasing properties. The result is a two-tiered gate oxide structure which is easily incorporated as a process module into any conventional EPROM or EEPROM process flow.
Other prior art known to Applicant includes U.S. Pat. No. 4,698,787 of Mukherjee et al., which discloses an electrically erasable programmable memory device which is also programmed by hot electron injection onto a floating gate, and erased by Fowler-Nordheim Tunnelling to the source region. The effect of impurities and damage on the oxidation rate of silicon is discussed in "VLSI Technology" edited by Sze, M. C., McGraw Hill Book Company, 1983, pp. 145-149.